1. Field of the Invention
The present invention relates to a method for fault analysis in wafer production, and, in particular, to a method for fault analysis for use for the production of integrated semiconductor products.
2. Description of the Related Art
As a rule, integrated semiconductor products are fabricated with the aid of “wafers”. A wafer is usually subdivided into a multiplicity of “chips” which finally correspond to the integrated semiconductor products at the end of production, in particular, after the wafer has been sawn apart. In this case, the size of the individual chips and the number of chips per wafer are essentially prescribed by the design and the type of the semiconductor product to be fabricated. The design and the type of the semiconductor product to be fabricated furthermore determine what fabrication process is undergone by the wafer.
At the end of fabrication, the chips are finally tested to determine whether or not the chips function. As a rule, these tests are carried out before the wafer is sawn apart. In this connection, the ratio of functioning chips to the total number of chips fabricated is one of the essential parameters. This parameter substantially determines the economics of the production in its entirety.
Furthermore, the results of the tests are used for fault analyses. Thus, by way of example, the intention is to find out whether systematic faults occur during the fabrication or whether the design of the semiconductor product to be fabricated has systematic faults or weaknesses. If the presence of such a fault can be discerned, it would be desirable, of course, if the fault source could also be determined.
As a rule, the starting point for corresponding fault analyses is a “multiple chip analysis” (“multiple window analysis”) in which ever larger, fictitious chips are formed, in a plurality of steps, from the chips present on the wafer. Such a fictitious chip, which is composed of a predetermined number of adjacent real chips, is regarded as a functioning chip if all the real chips from which it is constructed function. By contrast, if just one of said real chips is faulty, then the fictitious chip is also regarded as faulty. From the data thus obtained, it is then possible, under specific model assumptions, to determine the “electrically effective defect density”, which is important for further-reaching analyses.
Unfortunately, a series of difficulties arise when employing the multiple chip analysis. Thus, misinterpretations occur, for example, in the case of specific, relatively regular arrangements of the faulty chips on the wafer (“declustered fails”) since such arrangements are generally not identified correctly. Furthermore, such regular arrangements, which are restricted only to a part of the wafer, can adversely affect the correct identification of “normal” fault arrangements (“clustered fails”) since a type of compensation can occur between declustered fails and clustered fails.
In practice, in order to determine the electrically effective defect density, it is often necessary to carry out a regression, which can in turn lead to faulty results. Furthermore, the results may depend on the number of steps which lead to the fictitious chips that become ever larger, and on the way in which the real chips are combined to form the fictitious chips. Furthermore, the number of fictitious chips is dependent on the number of real chips on the wafer.
In the production of integrated semiconductor products, a multiplicity of different integrated semiconductor products are usually fabricated simultaneously at one production site. This means that a multiplicity of wafers with chips of different sizes and with a different number of chips are processed simultaneously. Even if the different semiconductor products are fabricated by means of the same technology, i.e., by means of essentially the same fabrication method, the test results of different semiconductor products cannot be directly compared with one another on the basis of the analysis methods used to date. This means that it often takes a very long time before faults in the fabrication process can be identified.